The invention relates to the transfer of information to and from a memory array in a computer system.
In any computer system, the transfer of data to and from a memory array is a critical function. It is essential that the computer system guarantee the integrity of the data stored in and accessed from its memory array.
In some applications for computer systems, any errors can have a disastrous effect. In these applications, such as computer systems that control the operation of nuclear reactors, there is a need for fault tolerant systems. Typically, the memory arrays in these systems communicate with two separate but identical sets of digital logic. This use of multiple components guarantees an extremely low probability of undetected system errors.
In most computer systems, the integrity of data transferred to or from a memory array is monitored using an error detecting and/or correcting code (EDC or ECC). Whenever read or write data is transferred, the EDC or ECC data corresponding to that read or write data also is transferred. In these computer systems, EDC or ECC data that is received from the computer system or accessed from storage by the memory array is compared with another set of EDC or ECC data that is generated locally by the memory array using the read or write data that is being transferred. If the generated EDC or ECC data matches the received or stored EDC or ECC data, the probability of an undetected error being present in the read or write data is very low.
In fault tolerant systems, reliability of data can be further increased by transferring the same data using the two separate sets of components. Preferably, the logic in each set is isolated from faults that are likely to occur in the other set. In this way, undetected errors can be prevented by comparing the data transferred by one set of logic to the data transferred using the other set of logic.
Although these techniques are important in improving data integrity and preventing undetected errors from occurring, there also are reasons to minimize the number of lines and pins used in the computer system. In particular, the mechanical reliability of the system is reduced, and the amount of hardware and the system cost is increased, when separate lines and pins are added to the memory array to accomplish the functions described above.
Therefore, there is a need for a computer system in which the number of lines and pins used in communicating with a memory array is minimized. However, there also is a need for a computer system in which the reliability of data being transferred to and from the memory array is high and the probability of undetected errors is low as a result of the use of error detecting/correcting codes and/or the use of two separate sets of logic that communicate with the memory array.